module rw_field #(
    parameter WD   = 32,
    parameter RST  = {WD{1'b0}},
    parameter MODE = 0 //rtl first, cpu next
)(
    input  clk,
    input  rst_n,

    input  cpu_en,
    input  cpu_w_en,
    input  [WD -1:0]cpu_wdata,

    input  rtl_wen,
    input  [WD -1:0]rtl_wdata,

    output [WD -1:0]rdata
);

wire cpu_wen = cpu_en && cpu_w_en;
wire [WD -1:0]wdata = (MODE == 0 && rtl_wen) ? rtl_wdata :
                      (MODE == 1 && cpu_wen) ? cpu_wdata :
                      rtl_wen ? rtl_wdata : cpu_wdata;

reg [WD -1:0]field;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        field <= RST;
    else if(rtl_wen || cpu_wen)
        field <= wdata;
end

assign rdata = field;

endmodule
